1. Field of the Invention
The present invention relates to electronic devices and electronic device assemblies that have a substrate including a power plane and a ground plane, such as, for example, a printed circuit board. More particularly, the present invention relates to methods for suppressing noise in at least one of a power plane and a ground plane of a substrate, to substrates that include noise suppression structures configured to suppress electrical waves propagating through at least one of a power plane and a ground plane of the substrate, and to electronic device assemblies that include such substrates.
2. Discussion of Related Art
In the field of electronic devices and systems, individual devices or components are both structurally and electrically assembled using substantially planar structures that include conductive elements, such as traces, terminals, and vias, some of which are electrically isolated from others by a dielectric material.
For example, in a computer system, a microprocessor and a memory module each may be electrically and structurally coupled to a printed circuit board (i.e., a motherboard). The microprocessor and the memory module may communicate electrically with one another through conductive elements (e.g., traces, terminals, and vias) of the printed circuit board. In addition, the memory module itself may include a relatively smaller printed circuit board to which one or more semiconductor device packages may be both electrically and structurally coupled. This relatively smaller printed circuit board of the memory module may be configured to provide electrical communication between the one or more semiconductor device packages that are structurally and electrically coupled thereto and the motherboard of the computer system through conductive elements (e.g., vias, traces, and terminals) of the relatively small printed circuit board. Furthermore, each semiconductor device package of the memory module may include yet another printed circuit board (e.g., interposer substrate), which may be smaller than both the printed circuit board of the memory module and the motherboard of the computer system.
Substantially planar substrates that are used to both electrically and structurally couple together one or more electronic devices or components often include planar layers of electrically conductive material (i.e., planar conductors) separated by layers of dielectric material. A portion of at least some of the conductive layers may be patterned to form electrically conductive traces, which typically extend generally parallel to the plane of the substrate. Conductive traces formed in different layers may be electrically coupled using conductive vias, which typically extend generally perpendicular to the plane of the substrate. Furthermore, at least one planar layer of electrically conductive material may be configured as a “power plane,” and at least one planar layer of electrically conductive material may be configured as the “ground plane.”
In high-speed digital electronic systems, the performance of the power delivery system continues to play an ever-increasing role in the overall performance of the electrical system. Signals in digital electronic systems typically carry information by alternating between a high voltage level (which may be defined by the voltage of the power plane of a printed circuit board) and a low voltage level (which may be defined by the voltage of the ground plane of a printed circuit board).
An important aspect of the performance of a power delivery system of an electronic system is “power coupling.” Power coupling is a phenomenon that occurs when the consumption of power by one or more devices of the electronic system causes fluctuation in power consumption by another device of the electronic system. For example, in a memory module that includes n number of semiconductor device packages, in a worst case scenario, n−1 semiconductor device packages may switch to a power consumption mode substantially simultaneously. This simultaneous switching of devices may generate propagating waves in the power and/or ground plane. These propagating waves may cause a temporary, but significant, drop in the voltage of the power plane at the location of the one remaining semiconductor device package. These propagating electrical waves in the power and/or ground plane caused by the simultaneous switching of devices may be referred to as simultaneous switching noise (SSN).
Devices of an electronic system that generate simultaneous switching noise may be referred to as “aggressor” or “aggressive” devices, while devices of an electronic system that are affected by simultaneous switching noise may be referred to as “victim” devices.
Simultaneous switching noise may cause victim devices to fail to function correctly. Therefore, a power delivery system should suppress such power coupling as much as possible so as to achieve “power isolation” between the various power consuming devices or components of an electronic system, thereby minimizing the occurrence of simultaneous switching noise in the power delivery system. This principle may be especially important as the number of power consuming devices or components increases for a given electronic system. Moreover, as the operating frequency of an electronic device increases into the gigahertz (GHz) range, the power delivery system of the electronic device may be required to retain a high level of power isolation between components over a broad range of frequencies. For example, for an electronic device that is configured to operate at a frequency of 3.2 GHz, it may be necessary or desirable to ensure a satisfactory level of power isolation between the individual components of the device over a range of frequencies extending up to about 9.6 GHz, which corresponds to the third harmonic of the operating frequency.
Two general methods for achieving power isolation between the various power consuming devices or components of an electronic system have been presented in the art. The first method for achieving power isolation between the various power consuming devices or components of an electronic system may be referred to as the “split plane” method. Briefly, the split plane method involves forming “gaps” or “splits” in the power plane and/or the ground plane. These splits may be disposed between the various power consuming devices or components of an electronic system. The split plane method is described in, for example, U.S. Pat. No. 5,131,140 to Zimmer, Jason R. Miller, The Impact of Split Power Planes on Package Performance, 2001 IEEE Electronic Components and Technology Conference, and Joong-Ho Kim & Madhavan Swaminathan, Modeling of Irregular Shaped Power Distribution Planes Using Transmission Matrix Method, IEEE Transactions on Advanced Packaging, Volume 24, no. 3, August 2001. The split plane method, however, may negatively affect the integrity of electrical signals carried by conductive traces that extend over or under a split in the power and/or ground plane. For example, plane splits may cause signal reflection or generate resonance in traces that extend over or under a split in the power and/or ground plane. Furthermore, plane splits may increase crosstalk between adjacent traces that extend over or under a split in the power and/or ground plane.
The second method for achieving power isolation between the various power consuming devices or components of an electronic system may be referred to as the “bypass capacitor” method. Briefly, the bypass capacitor method involves providing bypass capacitors between the power plane and the ground plane at selected locations on a printed circuit board to suppress simultaneous switching noise. The bypass capacitor method is described in, for example, U.S. Pat. No. 6,385,565 to Anderson et al., U.S. Pat. No. 6,789,241 to Anderson et al., and U.S. Pat. No. 6,850,878 to Smith et al. In the bypass capacitor method, however, each bypass capacitor may be effective only over a narrow range of frequencies. Therefore, a large number of bypass capacitors may be required to suppress simultaneous switching noise over a broad range of frequencies. Furthermore, the performance of bypass capacitors may be relatively limited at higher frequencies.
In view of the above, it would be desirable to provide methods for suppressing simultaneous switching noise in power and/or ground planes over broad ranges of frequencies (including relatively high frequencies) while minimizing any negative affect to the integrity of electrical signals carried by traces extending parallel to the power and/or ground planes.